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| author | whitequark <whitequark@whitequark.org> | 2020-06-09 07:26:13 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-06-09 07:26:13 +0000 |
| commit | ef4e1594470b46eab6f311998511a5eee22a96d3 (patch) | |
| tree | 493fa7e235a288f357f0708c38a576355f4fb3d9 /backends/cxxrtl/Makefile.inc | |
| parent | 4351194e8ce94e7078b67a20e5fc92777d6cb3e6 (diff) | |
| download | yosys-ef4e1594470b46eab6f311998511a5eee22a96d3.tar.gz yosys-ef4e1594470b46eab6f311998511a5eee22a96d3.tar.bz2 yosys-ef4e1594470b46eab6f311998511a5eee22a96d3.zip | |
cxxrtl: ignore cell input signedness when it is irrelevant.
Before this commit, Verilog expressions like `x && 1` would result in
references to `logic_and_us` in generated CXXRTL code, which would
not compile. After this commit, since cells like that actually behave
the same regardless of signedness attributes, the signedness is
ignored, which also reduces the template instantiation pressure.
Diffstat (limited to 'backends/cxxrtl/Makefile.inc')
0 files changed, 0 insertions, 0 deletions