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| author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-04-17 06:23:03 +0000 |
|---|---|---|
| committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-04-17 06:23:03 +0000 |
| commit | 00d74f0b9ceecc7b60f50fddb3b6ab0c47701923 (patch) | |
| tree | 1689f29481eb5ac889427035b71b2bdc05aa4782 /backends/cxxrtl/cxxrtl.cc | |
| parent | 10a814f97808de8cce7e50a03f01832db66c263e (diff) | |
| download | yosys-00d74f0b9ceecc7b60f50fddb3b6ab0c47701923.tar.gz yosys-00d74f0b9ceecc7b60f50fddb3b6ab0c47701923.tar.bz2 yosys-00d74f0b9ceecc7b60f50fddb3b6ab0c47701923.zip | |
Set Verilog source location for explicit blocks (`begin` ... `end`).
Diffstat (limited to 'backends/cxxrtl/cxxrtl.cc')
0 files changed, 0 insertions, 0 deletions