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| author | whitequark <whitequark@whitequark.org> | 2020-08-12 20:02:18 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-08-12 20:02:18 +0000 |
| commit | a74a43d85d5dd078d3cf7f1a0ab725dc90e3e456 (patch) | |
| tree | d489f0906dbdfd3f586a940d345656760a432a22 /backends/cxxrtl/cxxrtl.h | |
| parent | 97daf612cbeb24698c542d0e9574bab99dd616b7 (diff) | |
| parent | 5829d16fcd9a7645ea22eee3a489499780acc79c (diff) | |
| download | yosys-a74a43d85d5dd078d3cf7f1a0ab725dc90e3e456.tar.gz yosys-a74a43d85d5dd078d3cf7f1a0ab725dc90e3e456.tar.bz2 yosys-a74a43d85d5dd078d3cf7f1a0ab725dc90e3e456.zip | |
Merge pull request #2340 from andy-knowles/cxxrtl-fix-alu-carryout
cxxrtl.h: Fix incorrect CarryOut in alu when Bits % 32 != 0 && Invert == False
Diffstat (limited to 'backends/cxxrtl/cxxrtl.h')
| -rw-r--r-- | backends/cxxrtl/cxxrtl.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/backends/cxxrtl/cxxrtl.h b/backends/cxxrtl/cxxrtl.h index f0d7b9fc7..e3c96d422 100644 --- a/backends/cxxrtl/cxxrtl.h +++ b/backends/cxxrtl/cxxrtl.h @@ -452,10 +452,11 @@ struct value : public expr_base<value<Bits>> { bool carry = CarryIn; for (size_t n = 0; n < result.chunks; n++) { result.data[n] = data[n] + (Invert ? ~other.data[n] : other.data[n]) + carry; + if (result.chunks - 1 == n) + result.data[result.chunks - 1] &= result.msb_mask; carry = (result.data[n] < data[n]) || (result.data[n] == data[n] && carry); } - result.data[result.chunks - 1] &= result.msb_mask; return {result, carry}; } |