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| author | whitequark <whitequark@whitequark.org> | 2020-09-02 16:03:35 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-09-02 18:00:12 +0000 |
| commit | c7b2f07edf0c6c00f8576c1b4796a30e7447e917 (patch) | |
| tree | fd17ac187ba7de8d88e9c3ed628f2bf0e2e873f1 /backends/cxxrtl/cxxrtl.h | |
| parent | b025ee0aa646268747c121c97cf0673eb06e632b (diff) | |
| download | yosys-c7b2f07edf0c6c00f8576c1b4796a30e7447e917.tar.gz yosys-c7b2f07edf0c6c00f8576c1b4796a30e7447e917.tar.bz2 yosys-c7b2f07edf0c6c00f8576c1b4796a30e7447e917.zip | |
cxxrtl: improve handling of FFs with async inputs (other than CLK).
Before this commit, the meaning of "sync def" included some flip-flop
cells but not others. There was no actual reason for this; it was
just poorly defined.
After this commit, a "sync def" means that a wire holds design state
because it is connected directly to a flip-flop output, and may never
be unbuffered. This is not affected by presence of async inputs.
Diffstat (limited to 'backends/cxxrtl/cxxrtl.h')
0 files changed, 0 insertions, 0 deletions