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| author | whitequark <whitequark@whitequark.org> | 2021-07-19 16:20:49 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2021-07-19 16:22:55 +0000 |
| commit | fc84f230011b5a2eab1eefc319e8646b3ca2f657 (patch) | |
| tree | addd3aaf811686be618034c4a179320946613acd /backends/cxxrtl/cxxrtl_capi.cc | |
| parent | 9af88951bca3de799b9af121a45ad8c8d41dab2e (diff) | |
| download | yosys-fc84f230011b5a2eab1eefc319e8646b3ca2f657.tar.gz yosys-fc84f230011b5a2eab1eefc319e8646b3ca2f657.tar.bz2 yosys-fc84f230011b5a2eab1eefc319e8646b3ca2f657.zip | |
cxxrtl: escape colon in variable names in VCD writer.
The following VCD file crashes GTKWave's VCD loader:
$var wire 1 ! x:1 $end
$enddefinitions $end
In practice, a colon can be a part of a variable name that is
translated from a Verilog function, something like:
update$func$.../hdl/hazard3_csr.v:350$2534.$result
Diffstat (limited to 'backends/cxxrtl/cxxrtl_capi.cc')
0 files changed, 0 insertions, 0 deletions