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| author | whitequark <whitequark@whitequark.org> | 2020-06-08 16:22:30 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-06-08 17:09:49 +0000 |
| commit | 9b39c6f7442a525c8dbfd94f1af65a0b606e648b (patch) | |
| tree | 7751701892c7b408469a4188e0f081e70cf59e8a /backends/cxxrtl/cxxrtl_capi.h | |
| parent | a0466e1a969a40a7e90f8bce244eba6cdc1f2c1c (diff) | |
| download | yosys-9b39c6f7442a525c8dbfd94f1af65a0b606e648b.tar.gz yosys-9b39c6f7442a525c8dbfd94f1af65a0b606e648b.tar.bz2 yosys-9b39c6f7442a525c8dbfd94f1af65a0b606e648b.zip | |
cxxrtl: emit debug information for alias wires.
Alias wires can represent a significant chunk of the design in highly
hierarchical designs; in Minerva SRAM, there are 273 member wires and
527 alias wires. Showing them in every hierarchy level significantly
improves usability.
Diffstat (limited to 'backends/cxxrtl/cxxrtl_capi.h')
0 files changed, 0 insertions, 0 deletions