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authorEddie Hung <eddieh@ece.ubc.ca>2019-03-19 08:52:31 -0700
committerEddie Hung <eddieh@ece.ubc.ca>2019-03-19 08:52:31 -0700
commit02e8dc7ad2e13a43a310d311302c6db8168e6c11 (patch)
treeaf43bf9735fe47b09dbd8807c63fe451eb82aaba /backends/edif/edif.cc
parent3e89cf68bdc4e9eeb55bd9450121f421bcdc554a (diff)
parent61f37706f93042c2d1f093dd9bfa717390911eb3 (diff)
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Merge https://github.com/YosysHQ/yosys into read_aiger
Diffstat (limited to 'backends/edif/edif.cc')
-rw-r--r--backends/edif/edif.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index 2d25f879d..7e30b67af 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -130,7 +130,7 @@ struct EdifBackend : public Backend {
bool port_rename = false;
bool attr_properties = false;
std::map<RTLIL::IdString, std::map<RTLIL::IdString, int>> lib_cell_ports;
- bool nogndvcc = false, gndvccy = true;
+ bool nogndvcc = false, gndvccy = false;
CellTypes ct(design);
EdifNames edif_names;