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author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:00:30 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:00:30 +0200 |
commit | a84cb0493566f8f5eb610c6d7b67dda85b0f227b (patch) | |
tree | e4b1c2f97db2c317f8b986635141dfd7bb8e78d8 /backends/edif/edif.cc | |
parent | cd6574ecf652901573cbc6b89e1a59dd383ec496 (diff) | |
parent | f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 (diff) | |
download | yosys-a84cb0493566f8f5eb610c6d7b67dda85b0f227b.tar.gz yosys-a84cb0493566f8f5eb610c6d7b67dda85b0f227b.tar.bz2 yosys-a84cb0493566f8f5eb610c6d7b67dda85b0f227b.zip |
Merge automatic and manual code changes for new cell connections API
Diffstat (limited to 'backends/edif/edif.cc')
-rw-r--r-- | backends/edif/edif.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 13ab4dc62..fc2f4a7e4 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -148,7 +148,7 @@ struct EdifBackend : public Backend { RTLIL::Cell *cell = cell_it.second; if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) { lib_cell_ports[cell->type]; - for (auto p : cell->connections_) { + for (auto p : cell->connections()) { if (p.second.size() > 1) log_error("Found multi-bit port %s on library cell %s.%s (%s): not supported in EDIF backend!\n", RTLIL::id2cstr(p.first), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); @@ -304,7 +304,7 @@ struct EdifBackend : public Backend { fprintf(f, "\n (property %s (string \"%s\"))", EDIF_DEF(p.first), hex_string.c_str()); } fprintf(f, ")\n"); - for (auto &p : cell->connections_) { + for (auto &p : cell->connections()) { RTLIL::SigSpec sig = sigmap(p.second); for (int i = 0; i < SIZE(sig); i++) if (sig.size() == 1) |