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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-21 13:10:36 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-21 13:10:36 +0100 |
| commit | f3ff29d4107355f5a1941da67e6402644dffefa4 (patch) | |
| tree | 8e62696a26b9fcc8e3d27e896d183c3ed05a5eba /backends/edif/edif.cc | |
| parent | 3c5e9730924e5cc1ac5769f1fadd3f1d15a2aaa3 (diff) | |
| download | yosys-f3ff29d4107355f5a1941da67e6402644dffefa4.tar.gz yosys-f3ff29d4107355f5a1941da67e6402644dffefa4.tar.bz2 yosys-f3ff29d4107355f5a1941da67e6402644dffefa4.zip | |
Fixed instantiating multi-bit ports in edif backend
Diffstat (limited to 'backends/edif/edif.cc')
| -rw-r--r-- | backends/edif/edif.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 1748ed810..5020cd67e 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -303,8 +303,10 @@ struct EdifBackend : public Backend { sig.expand(); for (int i = 0; i < sig.width; i++) { RTLIL::SigSpec sigbit(sig.chunks.at(i)); - std::string portname = sig.width > 1 ? stringf("%s[%d]", RTLIL::id2cstr(p.first), i) : RTLIL::id2cstr(p.first); - net_join_db[sigbit].insert(stringf("(portRef %s (instanceRef %s))", edif_names(portname).c_str(), EDIF_NAME(cell->name))); + if (sig.width == 1) + net_join_db[sigbit].insert(stringf("(portRef %s (instanceRef %s))", edif_names(RTLIL::id2cstr(p.first)).c_str(), EDIF_NAME(cell->name))); + else + net_join_db[sigbit].insert(stringf("(portRef (member %s %d) (instanceRef %s))", edif_names(RTLIL::id2cstr(p.first)).c_str(), i, EDIF_NAME(cell->name))); } } } |