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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-22 15:01:12 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-22 15:01:12 +0100 |
| commit | 295e352ba6aa1bd71431abc21a8f93735968cae6 (patch) | |
| tree | 2261f6a66d6fa1e7f67d2aa220f6e4f588be4cea /backends/edif | |
| parent | c854ad2e7ecae6115182e9210f2b6c57afa98c23 (diff) | |
| download | yosys-295e352ba6aa1bd71431abc21a8f93735968cae6.tar.gz yosys-295e352ba6aa1bd71431abc21a8f93735968cae6.tar.bz2 yosys-295e352ba6aa1bd71431abc21a8f93735968cae6.zip | |
Renamed "placeholder" to "blackbox"
Diffstat (limited to 'backends/edif')
| -rw-r--r-- | backends/edif/edif.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 17ae08cce..c5977bb1d 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -121,7 +121,7 @@ struct EdifBackend : public Backend { for (auto module_it : design->modules) { RTLIL::Module *module = module_it.second; - if (module->get_bool_attribute("\\placeholder")) + if (module->get_bool_attribute("\\blackbox")) continue; if (top_module_name.empty()) @@ -135,7 +135,7 @@ struct EdifBackend : public Backend { for (auto cell_it : module->cells) { RTLIL::Cell *cell = cell_it.second; - if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\placeholder")) { + if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) { lib_cell_ports[cell->type]; for (auto p : cell->connections) { if (p.second.width > 1) @@ -233,7 +233,7 @@ struct EdifBackend : public Backend { fprintf(f, " (technology (numberDefinition))\n"); for (auto module : sorted_modules) { - if (module->get_bool_attribute("\\placeholder")) + if (module->get_bool_attribute("\\blackbox")) continue; SigMap sigmap(module); |