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| author | clairexen <claire@symbioticeda.com> | 2020-05-29 16:37:23 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-05-29 16:37:23 +0200 |
| commit | 94c10353897c6b2b3f960bdd6647a5da9c1d9f2c (patch) | |
| tree | 695ca7d8b26c8c4268498c76e09c157d9846bde0 /backends/firrtl/firrtl.cc | |
| parent | af36afe722dc35b129351af592ef340e512e0292 (diff) | |
| parent | f88bef767263590c94e157d0989afa91db3ccdb0 (diff) | |
| download | yosys-94c10353897c6b2b3f960bdd6647a5da9c1d9f2c.tar.gz yosys-94c10353897c6b2b3f960bdd6647a5da9c1d9f2c.tar.bz2 yosys-94c10353897c6b2b3f960bdd6647a5da9c1d9f2c.zip | |
Merge pull request #1885 from Xiretza/mod-rem-cells
Fix modulo/remainder semantics
Diffstat (limited to 'backends/firrtl/firrtl.cc')
| -rw-r--r-- | backends/firrtl/firrtl.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index a90b0b87a..b1d8500bb 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -585,6 +585,7 @@ struct FirrtlWorker firrtl_is_signed = a_signed | b_signed; firrtl_width = a_width; } else if (cell->type == ID($mod)) { + // "rem" = truncating modulo primop = "rem"; firrtl_width = min(a_width, b_width); } else if (cell->type.in(ID($and), ID($_AND_))) { |