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author | Clifford Wolf <clifford@clifford.at> | 2013-09-03 19:10:11 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-09-03 19:10:11 +0200 |
commit | 73914d1a414ad2277beca87fe1c52a564a796481 (patch) | |
tree | 7c3f53c65456a3ae5ad037e5b949aa8c36e30ec8 /backends/intersynth/intersynth.cc | |
parent | 5059b3166098044a87b3d0b7f3ae2957df7e6194 (diff) | |
download | yosys-73914d1a414ad2277beca87fe1c52a564a796481.tar.gz yosys-73914d1a414ad2277beca87fe1c52a564a796481.tar.bz2 yosys-73914d1a414ad2277beca87fe1c52a564a796481.zip |
Added -selected option to various backends
Diffstat (limited to 'backends/intersynth/intersynth.cc')
-rw-r--r-- | backends/intersynth/intersynth.cc | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index e0092ef18..513c17531 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -69,6 +69,10 @@ struct IntersynthBackend : public Backend { log(" inputs or outputs. This option can be used multiple times to specify\n"); log(" more than one library.\n"); log("\n"); + log(" -selected\n"); + log(" only write selected modules. modules must be selected entirely or\n"); + log(" not at all.\n"); + log("\n"); log("http://www.clifford.at/intersynth/\n"); log("\n"); } @@ -80,6 +84,7 @@ struct IntersynthBackend : public Backend { std::vector<std::string> libfiles; std::vector<RTLIL::Design*> libs; bool flag_notypes = false; + bool selected = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -92,6 +97,10 @@ struct IntersynthBackend : public Backend { libfiles.push_back(args[++argidx]); continue; } + if (args[argidx] == "-selected") { + selected = true; + continue; + } break; } extra_args(f, filename, args, argidx); @@ -123,9 +132,17 @@ struct IntersynthBackend : public Backend { RTLIL::Module *module = module_it.second; SigMap sigmap(module); + if (module->attributes.count("\\placeholder") > 0) + continue; if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells.size() == 0) continue; + if (selected && !design->selected_whole_module(module->name)) { + if (design->selected_module(module->name)) + log_cmd_error("Can't handle partially selected module %s!\n", RTLIL::id2cstr(module->name)); + continue; + } + log("Generating netlist %s.\n", RTLIL::id2cstr(module->name)); if (module->memories.size() != 0 || module->processes.size() != 0) |