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| author | Clifford Wolf <clifford@clifford.at> | 2019-01-27 09:23:41 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-01-27 09:23:41 +0100 |
| commit | 81581f24fc88ec67093c330d145bb52badead85d (patch) | |
| tree | af32198ad2adf19f1a265b90df357564d9448b34 /backends/intersynth/intersynth.cc | |
| parent | bf798a9020f1a8281f42f7f69d8d05d9e75114cb (diff) | |
| parent | 3d7925ad9f7840d5269b84d053ae808f36ccf762 (diff) | |
| download | yosys-81581f24fc88ec67093c330d145bb52badead85d.tar.gz yosys-81581f24fc88ec67093c330d145bb52badead85d.tar.bz2 yosys-81581f24fc88ec67093c330d145bb52badead85d.zip | |
Merge pull request #800 from whitequark/write_verilog_tribuf
write_verilog: write $tribuf cell as ternary
Diffstat (limited to 'backends/intersynth/intersynth.cc')
0 files changed, 0 insertions, 0 deletions