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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-18 09:00:06 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-18 09:00:06 -0700 |
| commit | 8fe0a961b306ef0c9c5de912833c6d92aed5f363 (patch) | |
| tree | 10325fb4b9a5d9a481177f0360fdbb8026e66367 /backends/intersynth/intersynth.cc | |
| parent | a20ed260e1b12da64bc4b40682c53145f6ffe827 (diff) | |
| parent | f4abc21d8ad79621cc24852bd76abf40a9d9f702 (diff) | |
| download | yosys-8fe0a961b306ef0c9c5de912833c6d92aed5f363.tar.gz yosys-8fe0a961b306ef0c9c5de912833c6d92aed5f363.tar.bz2 yosys-8fe0a961b306ef0c9c5de912833c6d92aed5f363.zip | |
Merge remote-tracking branch 'origin/clifford/whitebox' into xaig
Diffstat (limited to 'backends/intersynth/intersynth.cc')
| -rw-r--r-- | backends/intersynth/intersynth.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 2eb08dbe9..b0e3cd252 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -127,7 +127,7 @@ struct IntersynthBackend : public Backend { RTLIL::Module *module = module_it.second; SigMap sigmap(module); - if (module->get_bool_attribute("\\blackbox")) + if (module->get_blackbox_attribute()) continue; if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells_.size() == 0) continue; |