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| author | whitequark <whitequark@whitequark.org> | 2020-04-21 13:59:42 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-04-21 13:59:42 +0000 |
| commit | 12c5e9275c115104896d3c53f0bbdf3fc0c6f37d (patch) | |
| tree | 24491a1b8a9eb44e6804a60c83ccb53736d788c7 /backends/intersynth | |
| parent | 757cbb3c809091bf20a2f3b3a8b621010de01a8d (diff) | |
| download | yosys-12c5e9275c115104896d3c53f0bbdf3fc0c6f37d.tar.gz yosys-12c5e9275c115104896d3c53f0bbdf3fc0c6f37d.tar.bz2 yosys-12c5e9275c115104896d3c53f0bbdf3fc0c6f37d.zip | |
cxxrtl: simplify generated edge detection logic.
This commit changes the way edge detectors are represented in
generated code from a variable that is set in commit() and reset in
eval() to a function that considers .curr and .next of the clock
wire. Behavior remains the same. Besides being simpler to generate
and providing more opportunities for optimization, this commit paves
way for unbuffering module inputs.
Diffstat (limited to 'backends/intersynth')
0 files changed, 0 insertions, 0 deletions