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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-04-11 16:03:19 +0200 |
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| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-04-15 17:17:48 +0200 |
| commit | 53ba3cf7188883a9ef1c6c506c7b3a842dccc87b (patch) | |
| tree | a974fe8ddee04385fef434ea44f53e6f4a0f0d5e /backends/smt2/smtbmc.py | |
| parent | 7ad8b242806357599cfcbd228cef5c331935ef7c (diff) | |
| download | yosys-53ba3cf7188883a9ef1c6c506c7b3a842dccc87b.tar.gz yosys-53ba3cf7188883a9ef1c6c506c7b3a842dccc87b.tar.bz2 yosys-53ba3cf7188883a9ef1c6c506c7b3a842dccc87b.zip | |
Fix the truth table for $_SR_* cells.
This brings the documented behavior for these cells in line with
$_DFFSR_* and $_DLATCHSR_*, which is that R has priority over S.
The models were already reflecting that behavior.
Also get rid of sim-synth mismatch in the models while we're at it.
Diffstat (limited to 'backends/smt2/smtbmc.py')
0 files changed, 0 insertions, 0 deletions