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author | Clifford Wolf <clifford@clifford.at> | 2018-08-15 13:35:41 +0200 |
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committer | GitHub <noreply@github.com> | 2018-08-15 13:35:41 +0200 |
commit | 3d27c1cc80da1c631bf5eb9c0b6b27e74ca73873 (patch) | |
tree | 571f3835d5202c2540eed44b342ff187a65ce13b /backends/smt2/smtio.py | |
parent | d71529baa1deb224ab520b2431b2c1a176170054 (diff) | |
parent | 73d426bc879087ca522ca595a8ba921b647fae27 (diff) | |
download | yosys-3d27c1cc80da1c631bf5eb9c0b6b27e74ca73873.tar.gz yosys-3d27c1cc80da1c631bf5eb9c0b6b27e74ca73873.tar.bz2 yosys-3d27c1cc80da1c631bf5eb9c0b6b27e74ca73873.zip |
Merge pull request #513 from udif/pr_reg_wire_error
Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
Diffstat (limited to 'backends/smt2/smtio.py')
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