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author | Miodrag Milanović <mmicko@gmail.com> | 2023-01-23 16:55:17 +0100 |
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committer | GitHub <noreply@github.com> | 2023-01-23 16:55:17 +0100 |
commit | 8180cc4325a6650ef3f8c89c20e845b59cd9bc42 (patch) | |
tree | 9b21825f55813c58910ed23f45adc2570a2bd2c3 /backends/smt2/ywio.py | |
parent | 245884a1011fe45b00bbb9cacd0111eb014adadf (diff) | |
parent | d6c7aa0e3d9e64827a8305610bedcc9a9df88a49 (diff) | |
download | yosys-8180cc4325a6650ef3f8c89c20e845b59cd9bc42.tar.gz yosys-8180cc4325a6650ef3f8c89c20e845b59cd9bc42.tar.bz2 yosys-8180cc4325a6650ef3f8c89c20e845b59cd9bc42.zip |
Merge pull request #3624 from jix/sim_yw
Changes to support SBY trace generation with the sim command
Diffstat (limited to 'backends/smt2/ywio.py')
-rw-r--r-- | backends/smt2/ywio.py | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/backends/smt2/ywio.py b/backends/smt2/ywio.py index 8469b4162..39cfac41e 100644 --- a/backends/smt2/ywio.py +++ b/backends/smt2/ywio.py @@ -175,8 +175,9 @@ class WitnessSig: return self.sort_key < other.sort_key -def coalesce_signals(signals): - bits = {} +def coalesce_signals(signals, bits=None): + if bits is None: + bits = {} for sig in signals: for bit in sig.bits(): if sig.init_only: |