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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-24 22:47:57 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-24 23:10:58 +0200 |
| commit | 6aa792c864444324a1b140c2b63bd860f0cc3914 (patch) | |
| tree | 07b2bf3003864337df616a21374c046ddc352c62 /backends/spice/spice.cc | |
| parent | 7a608437c65e9646ed229055d61b310e7d93e37e (diff) | |
| download | yosys-6aa792c864444324a1b140c2b63bd860f0cc3914.tar.gz yosys-6aa792c864444324a1b140c2b63bd860f0cc3914.tar.bz2 yosys-6aa792c864444324a1b140c2b63bd860f0cc3914.zip | |
Replaced more old SigChunk programming patterns
Diffstat (limited to 'backends/spice/spice.cc')
| -rw-r--r-- | backends/spice/spice.cc | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 8e894cafd..e548df361 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -25,18 +25,17 @@ #include <string> #include <assert.h> -static void print_spice_net(FILE *f, RTLIL::SigSpec s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter) +static void print_spice_net(FILE *f, RTLIL::SigBit s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter) { - log_assert(s.chunks().size() == 1 && s.chunks()[0].width == 1); - if (s.chunks()[0].wire) { - if (s.chunks()[0].wire->width > 1) - fprintf(f, " %s[%d]", RTLIL::id2cstr(s.chunks()[0].wire->name), s.chunks()[0].offset); + if (s.wire) { + if (s.wire->width > 1) + fprintf(f, " %s[%d]", RTLIL::id2cstr(s.wire->name), s.offset); else - fprintf(f, " %s", RTLIL::id2cstr(s.chunks()[0].wire->name)); + fprintf(f, " %s", RTLIL::id2cstr(s.wire->name)); } else { - if (s.chunks()[0].data.bits.at(0) == RTLIL::State::S0) + if (s == RTLIL::State::S0) fprintf(f, " %s", neg.c_str()); - else if (s.chunks()[0].data.bits.at(0) == RTLIL::State::S1) + else if (s == RTLIL::State::S1) fprintf(f, " %s", pos.c_str()); else fprintf(f, " %s%d", ncpf.c_str(), nc_counter++); @@ -92,7 +91,6 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de for (auto &sig : port_sigs) { for (int i = 0; i < sig.size(); i++) { RTLIL::SigSpec s = sig.extract(big_endian ? sig.size() - 1 - i : i, 1); - log_assert(s.chunks().size() == 1 && s.chunks()[0].width == 1); print_spice_net(f, s, neg, pos, ncpf, nc_counter); } } |