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| author | Clifford Wolf <clifford@clifford.at> | 2014-11-09 10:44:23 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-11-09 10:44:23 +0100 |
| commit | fe829bdbdc436f425e082ab1cc8c3d276f168945 (patch) | |
| tree | 5d73123ffc07ec247e095c76f65bd4800f567d1b /backends/spice/spice.cc | |
| parent | cb9e10b4624e6ba6fff215766790e3ff3b82e9a8 (diff) | |
| download | yosys-fe829bdbdc436f425e082ab1cc8c3d276f168945.tar.gz yosys-fe829bdbdc436f425e082ab1cc8c3d276f168945.tar.bz2 yosys-fe829bdbdc436f425e082ab1cc8c3d276f168945.zip | |
Added log_warning() API
Diffstat (limited to 'backends/spice/spice.cc')
| -rw-r--r-- | backends/spice/spice.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 2aff94198..390822ed3 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -58,7 +58,7 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De if (design->modules_.count(cell->type) == 0) { - log("Warning: no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n", + log_warning("no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n", RTLIL::id2cstr(cell->type), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name)); for (auto &conn : cell->connections()) { RTLIL::SigSpec sig = sigmap(conn.second); |