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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-28 14:25:03 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-28 14:25:03 +0200 |
| commit | 27a872d1e7041be4894bc643a420587ff5894125 (patch) | |
| tree | 430d0411eaa4c4f6893576e2179d2eee93726def /backends/verilog/Makefile.inc | |
| parent | 3c45277ee0f5822181c6058f679de632f834e7d2 (diff) | |
| download | yosys-27a872d1e7041be4894bc643a420587ff5894125.tar.gz yosys-27a872d1e7041be4894bc643a420587ff5894125.tar.bz2 yosys-27a872d1e7041be4894bc643a420587ff5894125.zip | |
Added support for "upto" wires to Verilog front- and back-end
Diffstat (limited to 'backends/verilog/Makefile.inc')
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