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| author | whitequark <whitequark@whitequark.org> | 2019-01-02 09:36:32 +0000 |
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| committer | whitequark <whitequark@whitequark.org> | 2019-01-02 09:36:32 +0000 |
| commit | 06143ab33f4064677586be2a2b0d763f0818e856 (patch) | |
| tree | 693df3871bc11c1ed222bed63d0d52e6fe9bab97 /backends/verilog/verilog_backend.cc | |
| parent | f7363ac5086ccb8bdb97dcdbfed890c54e1ed153 (diff) | |
| download | yosys-06143ab33f4064677586be2a2b0d763f0818e856.tar.gz yosys-06143ab33f4064677586be2a2b0d763f0818e856.tar.bz2 yosys-06143ab33f4064677586be2a2b0d763f0818e856.zip | |
opt_lut: use a worklist, and revisit cells affected by elimination.
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
0 files changed, 0 insertions, 0 deletions