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authorMarcelina Koƛcielnicka <mwk@0x04.net>2020-10-25 23:01:59 +0100
committerMarcelina Koƛcielnicka <mwk@0x04.net>2021-05-27 15:53:12 +0200
commit1eae6025e7dccc021dcd2a6d658dae40ab02ef9e (patch)
treed3b3acd655f33637b767c634b4cb6be81b97ac57 /backends/verilog/verilog_backend.cc
parentb019db1f373e6bfe2b55363d28b9b6828a1cca6c (diff)
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memory_share: Improve same-address merging, recognize wide write ports.
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