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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2020-10-25 23:01:59 +0100 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-05-27 15:53:12 +0200 |
commit | 1eae6025e7dccc021dcd2a6d658dae40ab02ef9e (patch) | |
tree | d3b3acd655f33637b767c634b4cb6be81b97ac57 /backends/verilog/verilog_backend.cc | |
parent | b019db1f373e6bfe2b55363d28b9b6828a1cca6c (diff) | |
download | yosys-1eae6025e7dccc021dcd2a6d658dae40ab02ef9e.tar.gz yosys-1eae6025e7dccc021dcd2a6d658dae40ab02ef9e.tar.bz2 yosys-1eae6025e7dccc021dcd2a6d658dae40ab02ef9e.zip |
memory_share: Improve same-address merging, recognize wide write ports.
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
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