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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-03-16 14:35:39 +0100 |
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| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-03-16 14:35:39 +0100 |
| commit | 1f3423cd7d72d764217378200d7d1bd5ab721112 (patch) | |
| tree | 7b3cea53f2619a8f4d91de7a90e74500cd895c45 /backends/verilog/verilog_backend.cc | |
| parent | e217e3017af101bfe43d44c2e3afda3d5c2e0832 (diff) | |
| download | yosys-1f3423cd7d72d764217378200d7d1bd5ab721112.tar.gz yosys-1f3423cd7d72d764217378200d7d1bd5ab721112.tar.bz2 yosys-1f3423cd7d72d764217378200d7d1bd5ab721112.zip | |
Recognize registers and set initial state for them in tb
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
0 files changed, 0 insertions, 0 deletions