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| author | Clifford Wolf <clifford@clifford.at> | 2015-04-09 13:37:07 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-09 13:37:07 +0200 |
| commit | 229825e1b8936bd346829cf0ec9cf1fb3a67fc19 (patch) | |
| tree | 818b40a9362b445de1dc247486d9d87a34b2b2cf /backends/verilog/verilog_backend.cc | |
| parent | 25781e329b51ca84e5fd697705cb0377af64f90b (diff) | |
| download | yosys-229825e1b8936bd346829cf0ec9cf1fb3a67fc19.tar.gz yosys-229825e1b8936bd346829cf0ec9cf1fb3a67fc19.tar.bz2 yosys-229825e1b8936bd346829cf0ec9cf1fb3a67fc19.zip | |
Xilinx DRAMS: RAM64X1D, RAM128X1D
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
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