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| author | whitequark <whitequark@whitequark.org> | 2020-11-25 02:48:10 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-11-25 02:48:10 +0000 |
| commit | 2a39c785a210be8c0386e6f6d1a2cf2e4fc67589 (patch) | |
| tree | d3004a110b55a779a3e498303708a9d1a445b74c /backends/verilog/verilog_backend.cc | |
| parent | 88c47a380bdd62b633b11d1e763e7bcfd54ef423 (diff) | |
| parent | cdc802e4b77e6fecd250850c99469b81c2c7f104 (diff) | |
| download | yosys-2a39c785a210be8c0386e6f6d1a2cf2e4fc67589.tar.gz yosys-2a39c785a210be8c0386e6f6d1a2cf2e4fc67589.tar.bz2 yosys-2a39c785a210be8c0386e6f6d1a2cf2e4fc67589.zip | |
Merge pull request #2450 from nitz/sim-vcd-filename
Add rewrite_filename for sim -vcd argument.
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
0 files changed, 0 insertions, 0 deletions