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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-24 00:13:27 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-24 00:13:27 +0100 |
| commit | 43951099cf46b5a0a25bdebb001685a89dfe6c82 (patch) | |
| tree | b95a7ef79401216e1e65b30691b4ecaa2e7491af /backends/verilog/verilog_backend.cc | |
| parent | 1cb4c925d03de289f37a40b6eceb57ced8dce295 (diff) | |
| download | yosys-43951099cf46b5a0a25bdebb001685a89dfe6c82.tar.gz yosys-43951099cf46b5a0a25bdebb001685a89dfe6c82.tar.bz2 yosys-43951099cf46b5a0a25bdebb001685a89dfe6c82.zip | |
Added dict/pool.sort()
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index e9f4691b0..ab0844d72 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1137,6 +1137,8 @@ struct VerilogBackend : public Backend { } extra_args(f, filename, args, argidx); + design->sort(); + *f << stringf("/* Generated by %s */\n", yosys_version_str); for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) { if (it->second->get_bool_attribute("\\blackbox") != blackboxes) |