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| author | Catherine <whitequark@whitequark.org> | 2021-12-11 15:38:43 +0000 |
|---|---|---|
| committer | Catherine <whitequark@whitequark.org> | 2021-12-11 16:40:06 +0000 |
| commit | 55c9fb3b18cee0e2171486f9d4dfbd9b9e106354 (patch) | |
| tree | f3d7b963bdb7a4adc4efb9eea4900ec8d31464f7 /backends/verilog/verilog_backend.cc | |
| parent | 7c9e498662c378ea5e20aebd14918ac3d8df7c05 (diff) | |
| download | yosys-55c9fb3b18cee0e2171486f9d4dfbd9b9e106354.tar.gz yosys-55c9fb3b18cee0e2171486f9d4dfbd9b9e106354.tar.bz2 yosys-55c9fb3b18cee0e2171486f9d4dfbd9b9e106354.zip | |
cxxrtl: preserve interior memory pointers across reset.
Before this commit, values, wires, and memories with an initializer
were value-initialized in emitted C++ code. After this commit, all
values, wires, and memories are default-initialized, and the default
constructor of generated modules calls the reset() method, which
assigns the members that have an initializer.
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
0 files changed, 0 insertions, 0 deletions