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| author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-08-07 10:14:45 -0700 |
|---|---|---|
| committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-08-07 10:14:45 -0700 |
| commit | 5e8a98c8fd5f31b514748676804dd1237bce4225 (patch) | |
| tree | ead2b0029b55e078abc1023c434b87b4684ba498 /backends/verilog/verilog_backend.cc | |
| parent | 7e298084e458c3fcccece565df305271db51aec8 (diff) | |
| parent | 5545cd3c108ef240ccf6278b2734412acf81cd2a (diff) | |
| download | yosys-5e8a98c8fd5f31b514748676804dd1237bce4225.tar.gz yosys-5e8a98c8fd5f31b514748676804dd1237bce4225.tar.bz2 yosys-5e8a98c8fd5f31b514748676804dd1237bce4225.zip | |
Merge branch 'master' into firrtl_err_on_unsupported_cell
# Conflicts:
# backends/firrtl/firrtl.cc
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index e0b3a6f80..776f4eacb 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -558,6 +558,20 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } + if (cell->type == "$_NMUX_") { + f << stringf("%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->getPort("\\Y")); + f << stringf(" = !("); + dump_cell_expr_port(f, cell, "S", false); + f << stringf(" ? "); + dump_attributes(f, "", cell->attributes, ' '); + dump_cell_expr_port(f, cell, "B", false); + f << stringf(" : "); + dump_cell_expr_port(f, cell, "A", false); + f << stringf(");\n"); + return true; + } + if (cell->type.in("$_AOI3_", "$_OAI3_")) { f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Y")); |