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| author | Clifford Wolf <clifford@clifford.at> | 2015-07-02 11:14:30 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-07-02 11:14:30 +0200 |
| commit | 6c84341f22b2758181164e8d5cddd23e3589c90b (patch) | |
| tree | 0438ad9becf956e43ebf8665fee89e021b13bcdf /backends/verilog/verilog_backend.cc | |
| parent | 053058d78167f7f1ec377fddcee8b648a5ae4138 (diff) | |
| download | yosys-6c84341f22b2758181164e8d5cddd23e3589c90b.tar.gz yosys-6c84341f22b2758181164e8d5cddd23e3589c90b.tar.bz2 yosys-6c84341f22b2758181164e8d5cddd23e3589c90b.zip | |
Fixed trailing whitespaces
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index d160ec034..9b8064611 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -967,7 +967,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) } } // Output verilog that looks something like this: - // reg [..] _3_; + // reg [..] _3_; // always @(posedge CLK2) begin // _3_ <= memory[D1ADDR]; // if (A1EN) @@ -1011,7 +1011,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } - + // FIXME: $_SR_[PN][PN]_, $_DLATCH_[PN]_, $_DLATCHSR_[PN][PN][PN]_ // FIXME: $sr, $dlatch, $memrd, $memwr, $fsm |