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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:11:28 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:11:28 +0200 |
| commit | 97a59851a6c411ccb06162d4b31725bf89262378 (patch) | |
| tree | 74cba570ab858657b6fa524cdc9fa45b0493c4be /backends/verilog/verilog_backend.cc | |
| parent | a84cb0493566f8f5eb610c6d7b67dda85b0f227b (diff) | |
| download | yosys-97a59851a6c411ccb06162d4b31725bf89262378.tar.gz yosys-97a59851a6c411ccb06162d4b31725bf89262378.tar.bz2 yosys-97a59851a6c411ccb06162d4b31725bf89262378.zip | |
Added RTLIL::Cell::has(portname)
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 6bef90e38..d9186c043 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -301,7 +301,7 @@ void dump_cell_expr_port(FILE *f, RTLIL::Cell *cell, std::string port, bool gen_ std::string cellname(RTLIL::Cell *cell) { - if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->connections().count("\\Q") > 0) + if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->has("\\Q")) { RTLIL::SigSpec sig = cell->get("\\Q"); if (SIZE(sig) != 1 || sig.is_fully_const()) @@ -908,7 +908,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) for (auto &it : module->cells) { RTLIL::Cell *cell = it.second; - if (!reg_ct.cell_known(cell->type) || cell->connections().count("\\Q") == 0) + if (!reg_ct.cell_known(cell->type) || !cell->has("\\Q")) continue; RTLIL::SigSpec sig = cell->get("\\Q"); |