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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-21 14:24:50 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-21 14:24:50 -0700 |
| commit | a3371e118b05eb9bd5dddb1c20758674ae50a803 (patch) | |
| tree | 2293da584bc545d2b04948e2f5e28aad2d8b0cea /backends/verilog/verilog_backend.cc | |
| parent | e3f20b17afce26f08b277b757e32c33a473a8571 (diff) | |
| parent | f84a84e3f1a27b361c21fcd30fcf50c1a6586629 (diff) | |
| download | yosys-a3371e118b05eb9bd5dddb1c20758674ae50a803.tar.gz yosys-a3371e118b05eb9bd5dddb1c20758674ae50a803.tar.bz2 yosys-a3371e118b05eb9bd5dddb1c20758674ae50a803.zip | |
Merge branch 'master' into map_cells_before_map_luts
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 83d83f488..855409d0b 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1770,7 +1770,7 @@ struct VerilogBackend : public Backend { *f << stringf("/* Generated by %s */\n", yosys_version_str); for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) { - if (it->second->get_bool_attribute("\\blackbox") != blackboxes) + if (it->second->get_blackbox_attribute() != blackboxes) continue; if (selected && !design->selected_whole_module(it->first)) { if (design->selected_module(it->first)) |