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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 13:44:08 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 13:44:08 -0700 |
| commit | e3d898dccb3cf535a213f313693b2b7a4ede7c68 (patch) | |
| tree | ca5dfdf506a9a5bc37178eaa06f0d285b7649ff5 /backends/verilog/verilog_backend.cc | |
| parent | cdf9c801347693c273309694685b2080ef00fd02 (diff) | |
| parent | 3414ee1e3fe37d4bf383621542828d4fc8fc987f (diff) | |
| download | yosys-e3d898dccb3cf535a213f313693b2b7a4ede7c68.tar.gz yosys-e3d898dccb3cf535a213f313693b2b7a4ede7c68.tar.bz2 yosys-e3d898dccb3cf535a213f313693b2b7a4ede7c68.zip | |
Merge remote-tracking branch 'origin/master' into xc7dsp
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index e0b3a6f80..776f4eacb 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -558,6 +558,20 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } + if (cell->type == "$_NMUX_") { + f << stringf("%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->getPort("\\Y")); + f << stringf(" = !("); + dump_cell_expr_port(f, cell, "S", false); + f << stringf(" ? "); + dump_attributes(f, "", cell->attributes, ' '); + dump_cell_expr_port(f, cell, "B", false); + f << stringf(" : "); + dump_cell_expr_port(f, cell, "A", false); + f << stringf(");\n"); + return true; + } + if (cell->type.in("$_AOI3_", "$_OAI3_")) { f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Y")); |