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| author | Clifford Wolf <clifford@clifford.at> | 2019-01-02 14:47:18 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-01-02 14:47:18 +0100 |
| commit | 16bb823db8116ea2da2c659f8b9b2e9e2b9f2fbf (patch) | |
| tree | 61971fdccdc1bb24169d78d0193eccc957232536 /backends/verilog | |
| parent | 4b9f619349e6b7452739631635ab3b5a4d94b522 (diff) | |
| parent | efa278e232d20ea080743801bd91d55ec62955cf (diff) | |
| download | yosys-16bb823db8116ea2da2c659f8b9b2e9e2b9f2fbf.tar.gz yosys-16bb823db8116ea2da2c659f8b9b2e9e2b9f2fbf.tar.bz2 yosys-16bb823db8116ea2da2c659f8b9b2e9e2b9f2fbf.zip | |
Merge pull request #769 from whitequark/typos
Fix typographical and grammatical errors and inconsistencies
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 71db25f98..2537e18e5 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1447,7 +1447,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) } if (!module->processes.empty()) - log_warning("Module %s contains unmapped RTLIL proccesses. RTLIL processes\n" + log_warning("Module %s contains unmapped RTLIL processes. RTLIL processes\n" "can't always be mapped directly to Verilog always blocks. Unintended\n" "changes in simulation behavior are possible! Use \"proc\" to convert\n" "processes to logic networks and registers.\n", log_id(module)); |