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authorEddie Hung <eddie@fpgeh.com>2019-04-22 11:45:49 -0700
committerEddie Hung <eddie@fpgeh.com>2019-04-22 11:45:49 -0700
commit4486a98fd5928a4e3cdf9cd27c27b7dd821513bb (patch)
tree0afd22de8a09ab3995355e3813015c4523bd63fd /backends/verilog
parentcbb85e40e87fbfb1602bb934ed76a97efb9e55c6 (diff)
parentec88129a5cf510afc39ea12efa6059bed3eadfc3 (diff)
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Merge remote-tracking branch 'origin/xc7srl' into xc7mux
Diffstat (limited to 'backends/verilog')
-rw-r--r--backends/verilog/verilog_backend.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 83d83f488..855409d0b 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1770,7 +1770,7 @@ struct VerilogBackend : public Backend {
*f << stringf("/* Generated by %s */\n", yosys_version_str);
for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) {
- if (it->second->get_bool_attribute("\\blackbox") != blackboxes)
+ if (it->second->get_blackbox_attribute() != blackboxes)
continue;
if (selected && !design->selected_whole_module(it->first)) {
if (design->selected_module(it->first))