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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-08 15:40:37 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-08 15:40:37 -0800 |
| commit | 5f7349f26d814b8bf32a0e532b6f0fbacedcae90 (patch) | |
| tree | a35b021e5f9e593804ac536f221fd9c900d97b49 /backends/verilog | |
| parent | 6e3e81402520b854eb5879964adc3434fefd3f51 (diff) | |
| download | yosys-5f7349f26d814b8bf32a0e532b6f0fbacedcae90.tar.gz yosys-5f7349f26d814b8bf32a0e532b6f0fbacedcae90.tar.bz2 yosys-5f7349f26d814b8bf32a0e532b6f0fbacedcae90.zip | |
write_xaiger: holes PIs only if whitebox
Diffstat (limited to 'backends/verilog')
0 files changed, 0 insertions, 0 deletions