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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-20 17:24:06 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-20 17:24:06 -0700 |
| commit | 9dc11cd842952deca8e826b662f4565e2b52bd1d (patch) | |
| tree | 6caa919ebcb4618581d8dce4a43f98dbe585bda8 /backends/verilog | |
| parent | b25254020c7edc9e4d3fb2a24be5f029a09a1ee0 (diff) | |
| parent | f84a84e3f1a27b361c21fcd30fcf50c1a6586629 (diff) | |
| download | yosys-9dc11cd842952deca8e826b662f4565e2b52bd1d.tar.gz yosys-9dc11cd842952deca8e826b662f4565e2b52bd1d.tar.bz2 yosys-9dc11cd842952deca8e826b662f4565e2b52bd1d.zip | |
Merge remote-tracking branch 'origin/master' into xc7srl
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 83d83f488..855409d0b 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1770,7 +1770,7 @@ struct VerilogBackend : public Backend { *f << stringf("/* Generated by %s */\n", yosys_version_str); for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) { - if (it->second->get_bool_attribute("\\blackbox") != blackboxes) + if (it->second->get_blackbox_attribute() != blackboxes) continue; if (selected && !design->selected_whole_module(it->first)) { if (design->selected_module(it->first)) |