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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-26 03:07:51 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-27 14:32:51 +0200 |
| commit | b019db1f373e6bfe2b55363d28b9b6828a1cca6c (patch) | |
| tree | b6dbbd72a6691c384b71e17d721aa98163fbfd66 /backends/verilog | |
| parent | 83a218141c1a333b582c257c316ddea63e1ca519 (diff) | |
| download | yosys-b019db1f373e6bfe2b55363d28b9b6828a1cca6c.tar.gz yosys-b019db1f373e6bfe2b55363d28b9b6828a1cca6c.tar.bz2 yosys-b019db1f373e6bfe2b55363d28b9b6828a1cca6c.zip | |
kernel/mem: Add helpers for write port widening.
Diffstat (limited to 'backends/verilog')
0 files changed, 0 insertions, 0 deletions