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| author | whitequark <whitequark@whitequark.org> | 2020-12-15 03:46:06 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-12-15 11:02:38 +0000 |
| commit | d889a3df35e539b6dcfbee9c6a98461eca1a0b0e (patch) | |
| tree | 671f162b4944a1a4ed602bb85ba94f149a462170 /backends/verilog | |
| parent | f75bc6c7aac92c7c1c8954ec7fe5325a94e6e491 (diff) | |
| download | yosys-d889a3df35e539b6dcfbee9c6a98461eca1a0b0e.tar.gz yosys-d889a3df35e539b6dcfbee9c6a98461eca1a0b0e.tar.bz2 yosys-d889a3df35e539b6dcfbee9c6a98461eca1a0b0e.zip | |
cxxrtl: print names of cells inlined in connections.
Diffstat (limited to 'backends/verilog')
0 files changed, 0 insertions, 0 deletions