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| author | whitequark <whitequark@whitequark.org> | 2020-04-03 16:07:43 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-04-09 04:08:36 +0000 |
| commit | fb0270b75258fa58cbf0594873721c88964f69a5 (patch) | |
| tree | a4e54b82f161a8296eae872b0dd10c1ab3b69339 /backends/verilog | |
| parent | 3376dcf37c02f10552f84a9602b0d05c8f77ba3a (diff) | |
| download | yosys-fb0270b75258fa58cbf0594873721c88964f69a5.tar.gz yosys-fb0270b75258fa58cbf0594873721c88964f69a5.tar.bz2 yosys-fb0270b75258fa58cbf0594873721c88964f69a5.zip | |
write_cxxrtl: add support for hierarchical designs.
Hierarchical design simulations are generally much slower, but this
comes with a major increase in flexibility:
1. Since the `flatten` pass currently does not support flattening
of designs with processes, this is the only way to simulate such
designs with cxxrtl.
2. Support for hierarchy paves way for simulation black boxes,
which are necessary for e.g. replacing PHYs with C++ code that
integrates with the host system.
Diffstat (limited to 'backends/verilog')
0 files changed, 0 insertions, 0 deletions