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authorSahand Kashani <sahand.kashani@gmail.com>2020-03-19 14:59:05 +0100
committerSahand Kashani <sahand.kashani@gmail.com>2020-03-19 14:59:05 +0100
commit59236314f80b68126ca7ec81cca3ce1bf36a384b (patch)
treee5695abda5a65c51ff5eb5764df01a02a9019119 /backends
parentbdce9c28c2078077f279999bfa31f5adc5157774 (diff)
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Add fileinfo to firrtl backend for modules and wires
Diffstat (limited to 'backends')
-rw-r--r--backends/firrtl/firrtl.cc32
1 files changed, 20 insertions, 12 deletions
diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index 56a464b1e..30b99fd91 100644
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -96,6 +96,17 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
}
}
+std::string getFileinfo(dict<RTLIL::IdString, RTLIL::Const> attributes)
+{
+ std::ostringstream fileinfo;
+ for (auto &it : attributes) {
+ if (it.first == "\\src") {
+ dump_const(fileinfo, it.second);
+ }
+ }
+ return fileinfo.str();
+}
+
// Get a port direction with respect to a specific module.
FDirection getPortFDirection(IdString id, Module *module)
{
@@ -448,12 +459,15 @@ struct FirrtlWorker
void run()
{
- f << stringf(" module %s:\n", make_id(module->name));
+ auto moduleFileinfo = getFileinfo(module->attributes);
+ f << stringf(" module %s: @[%s]\n", make_id(module->name), moduleFileinfo.c_str());
vector<string> port_decls, wire_decls, cell_exprs, wire_exprs;
for (auto wire : module->wires())
{
const auto wireName = make_id(wire->name);
+ auto wireFileinfo = getFileinfo(wire->attributes);
+
// If a wire has initial data, issue a warning since FIRRTL doesn't currently support it.
if (wire->attributes.count("\\init")) {
log_warning("Initial value (%s) for (%s.%s) not supported\n",
@@ -464,12 +478,12 @@ struct FirrtlWorker
{
if (wire->port_input && wire->port_output)
log_error("Module port %s.%s is inout!\n", log_id(module), log_id(wire));
- port_decls.push_back(stringf(" %s %s: UInt<%d>\n", wire->port_input ? "input" : "output",
- wireName, wire->width));
+ port_decls.push_back(stringf(" %s %s: UInt<%d> @[%s]\n", wire->port_input ? "input" : "output",
+ wireName, wire->width, wireFileinfo.c_str()));
}
else
{
- wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", wireName, wire->width));
+ wire_decls.push_back(stringf(" wire %s: UInt<%d> @[%s]\n", wireName, wire->width, wireFileinfo.c_str()));
}
}
@@ -1177,14 +1191,8 @@ struct FirrtlBackend : public Backend {
if (top == nullptr)
top = last;
- std::ostringstream fileinfo;
- for (auto &it : top->attributes) {
- if (it.first == "\\src") {
- dump_const(fileinfo, it.second);
- }
- }
-
- *f << stringf("circuit %s: @[%s]\n", make_id(top->name), fileinfo.str().c_str());
+ auto circuitFileinfo = getFileinfo(top->attributes);
+ *f << stringf("circuit %s: @[%s]\n", make_id(top->name), circuitFileinfo.c_str());
for (auto module : design->modules())
{