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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 17:21:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 17:21:14 -0700 |
| commit | 7959e9d6b25d7afefded4b14e14ccf2b0b5af553 (patch) | |
| tree | 000580f4fe0ce2f3109b65534f6947c92c420681 /backends | |
| parent | 7a45cd58566310f623bd567a393beb8a734ebf60 (diff) | |
| download | yosys-7959e9d6b25d7afefded4b14e14ccf2b0b5af553.tar.gz yosys-7959e9d6b25d7afefded4b14e14ccf2b0b5af553.tar.bz2 yosys-7959e9d6b25d7afefded4b14e14ccf2b0b5af553.zip | |
Fix merge issues
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 09b5586fe..4547b9c09 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -254,7 +254,7 @@ struct XAigerWriter log_assert(!holes_mode); - if (cell->type == "$__ABC_FF_") + if (cell->type == "$__ABC9_FF_") { SigBit D = sigmap(cell->getPort("\\D").as_bit()); SigBit Q = sigmap(cell->getPort("\\Q").as_bit()); |