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author | Miodrag Milanovic <mmicko@gmail.com> | 2022-05-27 10:23:34 +0200 |
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committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-05-27 10:23:34 +0200 |
commit | 7ee570a75e876e0e7d73ad2ee54a0be92956c03d (patch) | |
tree | 73844b8bdadaa934a547dca19657bc70744ace14 /backends | |
parent | b0c71ed5945716e5719c09f73f056fc6a4834042 (diff) | |
download | yosys-7ee570a75e876e0e7d73ad2ee54a0be92956c03d.tar.gz yosys-7ee570a75e876e0e7d73ad2ee54a0be92956c03d.tar.bz2 yosys-7ee570a75e876e0e7d73ad2ee54a0be92956c03d.zip |
Use proper operator
Diffstat (limited to 'backends')
-rw-r--r-- | backends/firrtl/firrtl.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index 85c44824f..76ba77abb 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -729,12 +729,12 @@ struct FirrtlWorker always_uint = true; firrtl_width = max(a_width, b_width); } - else if ((cell->type == ID($eq)) | (cell->type == ID($eqx))) { + else if ((cell->type == ID($eq)) || (cell->type == ID($eqx))) { primop = "eq"; always_uint = true; firrtl_width = 1; } - else if ((cell->type == ID($ne)) | (cell->type == ID($nex))) { + else if ((cell->type == ID($ne)) || (cell->type == ID($nex))) { primop = "neq"; always_uint = true; firrtl_width = 1; @@ -759,7 +759,7 @@ struct FirrtlWorker always_uint = true; firrtl_width = 1; } - else if ((cell->type == ID($shl)) | (cell->type == ID($sshl))) { + else if ((cell->type == ID($shl)) || (cell->type == ID($sshl))) { // FIRRTL will widen the result (y) by the amount of the shift. // We'll need to offset this by extracting the un-widened portion as Verilog would do. extract_y_bits = true; @@ -777,7 +777,7 @@ struct FirrtlWorker firrtl_width = a_width + (1 << b_width) - 1; } } - else if ((cell->type == ID($shr)) | (cell->type == ID($sshr))) { + else if ((cell->type == ID($shr)) || (cell->type == ID($sshr))) { // We don't need to extract a specific range of bits. extract_y_bits = false; // Is the shift amount constant? |