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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-13 09:38:07 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
| commit | 95763c8d18eec49de3acff5d38a82f54cc25cb1b (patch) | |
| tree | 29350a6c58a7654873e31ac93c6248219a66dfc7 /backends | |
| parent | accfc70fc2bcfaa5f9f58e8a113a32e506f5081d (diff) | |
| download | yosys-95763c8d18eec49de3acff5d38a82f54cc25cb1b.tar.gz yosys-95763c8d18eec49de3acff5d38a82f54cc25cb1b.tar.bz2 yosys-95763c8d18eec49de3acff5d38a82f54cc25cb1b.zip | |
abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxes
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index d014c4ec6..2e2ca7018 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -616,7 +616,6 @@ struct XAigerWriter dict<SigBit, int> clk_to_mergeability; - bool nonzero_warned = false; for (const auto &i : ff_bits) { const SigBit &d = i.first; const Cell *cell = i.second; @@ -633,15 +632,10 @@ struct XAigerWriter write_r_buffer(mergeability); else log_abort(); - Const init = cell->attributes.at(ID::abc9_init, State::Sx); + Const init = cell->attributes.at(ID::abc9_init); log_assert(GetSize(init) == 1); - if (init == State::S1) { - if (!nonzero_warned) { - log_warning("Module '%s' contains $_DFF_[NP]_ cell with non-zero initial state -- unsupported by ABC9.\n", log_id(module)); - nonzero_warned = true; - } + if (init == State::S1) write_s_buffer(1); - } else if (init == State::S0) write_s_buffer(0); else { |