diff options
| author | Diego H <diego@symbioticeda.com> | 2019-12-12 13:40:05 -0600 |
|---|---|---|
| committer | Diego H <diego@symbioticeda.com> | 2019-12-12 13:40:05 -0600 |
| commit | ab6ac8327f28b2ba9530c81cdbb5091a1ef91032 (patch) | |
| tree | 9e2716d6d621eeeda85896b7b2993de517bb931a /backends | |
| parent | 3a5a65829cc593965304537ddcb4d6d1d3e3ca8b (diff) | |
| parent | 2666482282421bb54213ba01054111eadc401373 (diff) | |
| download | yosys-ab6ac8327f28b2ba9530c81cdbb5091a1ef91032.tar.gz yosys-ab6ac8327f28b2ba9530c81cdbb5091a1ef91032.tar.bz2 yosys-ab6ac8327f28b2ba9530c81cdbb5091a1ef91032.zip | |
Merge https://github.com/YosysHQ/yosys into bram_xilinx
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 46890b071..627133314 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -153,11 +153,6 @@ struct XAigerWriter if (wire->port_input) sigmap.add(wire); - // promote output wires - for (auto wire : module->wires()) - if (wire->port_output) - sigmap.add(wire); - for (auto wire : module->wires()) { bool keep = wire->attributes.count("\\keep"); @@ -173,7 +168,7 @@ struct XAigerWriter } if (keep) - keep_bits.insert(bit); + keep_bits.insert(wirebit); if (wire->port_input || keep) { if (bit != wirebit) @@ -824,7 +819,7 @@ struct XAigerBackend : public Backend { log(" write ASCII version of AIGER format\n"); log("\n"); log(" -map <filename>\n"); - log(" write an extra file with port and latch symbols\n"); + log(" write an extra file with port and box symbols\n"); log("\n"); log(" -vmap <filename>\n"); log(" like -map, but more verbose\n"); |