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| author | Claire Xen <claire@clairexen.net> | 2021-10-11 09:56:05 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-10-11 09:56:05 +0200 |
| commit | d5cc3a1c72085da29dcc2ef926f885421bb0f2a6 (patch) | |
| tree | 2d9721c9bbe89e918fe60cda445de5bd98e2dfe6 /backends | |
| parent | c15b99c0deea562dd7672b934567457a01836212 (diff) | |
| parent | ff8e999a7112a1975d268e6ebb3e751f6f0364c7 (diff) | |
| download | yosys-d5cc3a1c72085da29dcc2ef926f885421bb0f2a6.tar.gz yosys-d5cc3a1c72085da29dcc2ef926f885421bb0f2a6.tar.bz2 yosys-d5cc3a1c72085da29dcc2ef926f885421bb0f2a6.zip | |
Merge pull request #3040 from YosysHQ/micko/split_module_ports
Split module ports, 20 per line
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 6fb14d7fc..dc5c188c0 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -2062,6 +2062,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) dump_attributes(f, indent, module->attributes, '\n', /*modattr=*/true); f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str()); bool keep_running = true; + int cnt = 0; for (int port_id = 1; keep_running; port_id++) { keep_running = false; for (auto wire : module->wires()) { @@ -2070,6 +2071,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) f << stringf(", "); f << stringf("%s", id(wire->name).c_str()); keep_running = true; + if (cnt==20) { f << stringf("\n"); cnt = 0; } else cnt++; continue; } } |