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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-20 15:35:32 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-20 15:35:32 -0800 |
| commit | f89b112fbf19a751070406449ab78f07b2c5e639 (patch) | |
| tree | 66c2d9b02731141bf9c2dcab48f8c1cc3f4c147d /backends | |
| parent | 43d5471570bd208ec87e2994f53a835c1e8ef3b9 (diff) | |
| download | yosys-f89b112fbf19a751070406449ab78f07b2c5e639.tar.gz yosys-f89b112fbf19a751070406449ab78f07b2c5e639.tar.bz2 yosys-f89b112fbf19a751070406449ab78f07b2c5e639.zip | |
write_aiger: fix CI/CO and symbols
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/.xaiger.cc.swo | bin | 0 -> 36864 bytes | |||
| -rw-r--r-- | backends/aiger/xaiger.cc | 20 |
2 files changed, 13 insertions, 7 deletions
diff --git a/backends/aiger/.xaiger.cc.swo b/backends/aiger/.xaiger.cc.swo Binary files differnew file mode 100644 index 000000000..a12729835 --- /dev/null +++ b/backends/aiger/.xaiger.cc.swo diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index d125335f9..56d361fff 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -232,17 +232,22 @@ struct XAigerWriter co_bits.erase(bit); output_bits.erase(bit); } - // Erase all CIs that are also COs or POs - for (auto bit : co_bits) + // Erase all POs and CIs that are also PIs + for (auto bit : input_bits) { + output_bits.erase(bit); ci_bits.erase(bit); - for (auto bit : output_bits) + } + for (auto bit : output_bits) { + ci_bits.erase(bit); + // POs override COs + co_bits.erase(bit); + } + // Erase all CIs that are also COs + for (auto bit : co_bits) ci_bits.erase(bit); // CIs cannot be undriven for (auto bit : ci_bits) undriven_bits.erase(bit); - // POs override COs - for (auto bit : output_bits) - co_bits.erase(bit); for (auto bit : unused_bits) undriven_bits.erase(bit); @@ -525,7 +530,7 @@ struct XAigerWriter for (int i = 0; i < GetSize(wire); i++) { RTLIL::SigBit b(wire, i); - if (wire->port_input || ci_bits.count(b)) { + if (input_bits.count(b) || ci_bits.count(b)) { int a = aig_map.at(sig[i]); log_assert((a & 1) == 0); input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire)); @@ -567,6 +572,7 @@ struct XAigerWriter input_lines.sort(); for (auto &it : input_lines) f << it.second; + log_assert(input_lines.size() == input_bits.size() + ci_bits.size()); init_lines.sort(); for (auto &it : init_lines) |