Refactoring: Renamed RTLIL::Module::wires to wires_

8 files changed, 14 insertions, 14 deletions

diff --git a/backends/autotest/autotest.cc b/backends/autotest/autotest.cc
index db49880ae..06b2c2a93 100644
--- a/backends/autotest/autotest.cc
+++ b/backends/autotest/autotest.cc
@@ -105,7 +105,7 @@ static void autotest(FILE *f, RTLIL::Design *design)
 
 		int count_ports = 0;
 		log("Generating test bench for module `%s'.\n", it->first.c_str());
-		for (auto it2 = mod->wires.begin(); it2 != mod->wires.end(); it2++) {
+		for (auto it2 = mod->wires_.begin(); it2 != mod->wires_.end(); it2++) {
 			RTLIL::Wire *wire = it2->second;
 			if (wire->port_output) {
 				count_ports++;
@@ -134,7 +134,7 @@ static void autotest(FILE *f, RTLIL::Design *design)
 			}
 		}
 		fprintf(f, "%s %s(\n", id(mod->name).c_str(), idy("uut", mod->name).c_str());
-		for (auto it2 = mod->wires.begin(); it2 != mod->wires.end(); it2++) {
+		for (auto it2 = mod->wires_.begin(); it2 != mod->wires_.end(); it2++) {
 			RTLIL::Wire *wire = it2->second;
 			if (wire->port_output || wire->port_input)
 				fprintf(f, "\t.%s(%s)%s\n", id(wire->name).c_str(),
diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index cb40834b3..7ae9965d5 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -103,7 +103,7 @@ struct BlifDumper
 
 		std::map<int, RTLIL::Wire*> inputs, outputs;
 
-		for (auto &wire_it : module->wires) {
+		for (auto &wire_it : module->wires_) {
 			RTLIL::Wire *wire = wire_it.second;
 			if (wire->port_input)
 				inputs[wire->port_id] = wire;
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index f731e17e2..f1e95ee15 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -80,7 +80,7 @@ struct BtorDumper
 	{
 		line_num=0;
 		str.clear();
-		for(auto it=module->wires.begin(); it!=module->wires.end(); ++it)
+		for(auto it=module->wires_.begin(); it!=module->wires_.end(); ++it)
 		{
 			if(it->second->port_input)
 			{
@@ -880,7 +880,7 @@ struct BtorDumper
 		std::map<int, RTLIL::Wire*> inputs, outputs;
 		std::vector<RTLIL::Wire*> safety;
 		
-		for (auto &wire_it : module->wires) {
+		for (auto &wire_it : module->wires_) {
 			RTLIL::Wire *wire = wire_it.second;
 			if (wire->port_input)
 				inputs[wire->port_id] = wire;
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index fc2f4a7e4..e99d094f7 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -255,7 +255,7 @@ struct EdifBackend : public Backend {
 			fprintf(f, "      (view VIEW_NETLIST\n");
 			fprintf(f, "        (viewType NETLIST)\n");
 			fprintf(f, "        (interface\n");
-			for (auto &wire_it : module->wires) {
+			for (auto &wire_it : module->wires_) {
 				RTLIL::Wire *wire = wire_it.second;
 				if (wire->port_id == 0)
 					continue;
diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc
index 6678f19d2..c0b7dab9a 100644
--- a/backends/ilang/ilang_backend.cc
+++ b/backends/ilang/ilang_backend.cc
@@ -280,7 +280,7 @@ void ILANG_BACKEND::dump_module(FILE *f, std::string indent, const RTLIL::Module
 
 	if (print_body)
 	{
-		for (auto it = module->wires.begin(); it != module->wires.end(); it++)
+		for (auto it = module->wires_.begin(); it != module->wires_.end(); it++)
 			if (!only_selected || design->selected(module, it->second)) {
 				if (only_selected)
 					fprintf(f, "\n");
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index 8c08747c3..4e8c321bb 100644
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -147,7 +147,7 @@ struct IntersynthBackend : public Backend {
 			netlists_code += stringf("netlist %s\n", RTLIL::id2cstr(module->name));
 
 			// Module Ports: "std::set<string> celltypes_code" prevents duplicate top level ports
-			for (auto wire_it : module->wires) {
+			for (auto wire_it : module->wires_) {
 				RTLIL::Wire *wire = wire_it.second;
 				if (wire->port_input || wire->port_output) {
 					celltypes_code.insert(stringf("celltype !%s b%d %sPORT\n" "%s %s %d %s PORT\n",
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index 077368771..ef31e06a9 100644
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -68,7 +68,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
 			RTLIL::Module *mod = design->modules.at(cell->type);
 
 			std::vector<RTLIL::Wire*> ports;
-			for (auto wire_it : mod->wires) {
+			for (auto wire_it : mod->wires_) {
 				RTLIL::Wire *wire = wire_it.second;
 				if (wire->port_id == 0)
 					continue;
@@ -195,7 +195,7 @@ struct SpiceBackend : public Backend {
 			}
 
 			std::vector<RTLIL::Wire*> ports;
-			for (auto wire_it : module->wires) {
+			for (auto wire_it : module->wires_) {
 				RTLIL::Wire *wire = wire_it.second;
 				if (wire->port_id == 0)
 					continue;
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index d9186c043..5e98a4c54 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -76,7 +76,7 @@ void reset_auto_counter(RTLIL::Module *module)
 
 	reset_auto_counter_id(module->name, false);
 
-	for (auto it = module->wires.begin(); it != module->wires.end(); it++)
+	for (auto it = module->wires_.begin(); it != module->wires_.end(); it++)
 		reset_auto_counter_id(it->second->name, true);
 
 	for (auto it = module->cells.begin(); it != module->cells.end(); it++) {
@@ -920,7 +920,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module)
 						reg_bits.insert(std::pair<RTLIL::Wire*,int>(chunk.wire, chunk.offset+i));
 			}
 		}
-		for (auto &it : module->wires)
+		for (auto &it : module->wires_)
 		{
 			RTLIL::Wire *wire = it.second;
 			for (int i = 0; i < wire->width; i++)
@@ -936,7 +936,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module)
 	bool keep_running = true;
 	for (int port_id = 1; keep_running; port_id++) {
 		keep_running = false;
-		for (auto it = module->wires.begin(); it != module->wires.end(); it++) {
+		for (auto it = module->wires_.begin(); it != module->wires_.end(); it++) {
 			RTLIL::Wire *wire = it->second;
 			if (wire->port_id == port_id) {
 				if (port_id != 1)
@@ -949,7 +949,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module)
 	}
 	fprintf(f, ");\n");
 
-	for (auto it = module->wires.begin(); it != module->wires.end(); it++)
+	for (auto it = module->wires_.begin(); it != module->wires_.end(); it++)
 		dump_wire(f, indent + "  ", it->second);
 
 	for (auto it = module->memories.begin(); it != module->memories.end(); it++)