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| author | Dag Lem <dag@nimrod.no> | 2022-11-13 07:41:25 +0100 |
|---|---|---|
| committer | Dag Lem <dag@nimrod.no> | 2022-11-13 07:41:25 +0100 |
| commit | a862642fac5d5b7700b2e13829a411f2755273a0 (patch) | |
| tree | 0229fc5566a4035b244ca3bcae4068949da67811 /docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst | |
| parent | 553eb6ac1eb49085f979d7650d83b3b93298835a (diff) | |
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Correct interpretation of SystemVerilog C-style array dimensions
IEEE Std 1800™-2017 7.4.2 specifies that [size] is the same as [0:size-1].
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