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| author | Jannis Harder <me@jix.one> | 2022-11-23 15:12:17 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-11-23 15:12:17 +0100 |
| commit | fc2f622a27dbc604a4acce68bea8c20b208c1742 (patch) | |
| tree | a19dac08ea32661da5c418fae41756cbbb086164 /docs/source/appendix/APPNOTE_011_Design_Investigation.rst | |
| parent | 13e4f343b9818d1066e910f396fc634981fc07db (diff) | |
| parent | a862642fac5d5b7700b2e13829a411f2755273a0 (diff) | |
| download | yosys-fc2f622a27dbc604a4acce68bea8c20b208c1742.tar.gz yosys-fc2f622a27dbc604a4acce68bea8c20b208c1742.tar.bz2 yosys-fc2f622a27dbc604a4acce68bea8c20b208c1742.zip | |
Merge pull request #3552 from daglem/fix-sv-c-array-dimensions
Correct interpretation of SystemVerilog C-style array dimensions
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